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The Intelannounced inwas the first x87 floating-point coprocessor for the line of microprocessors. The purpose of the was to speed up computations for floating-point arithmetic, such as additionsubtractionmultiplicationdivisionand square root.
It also computed transcendental functions such as exponentiallogarithmic or trigonometric calculations, and besides floating-point it could also operate on large binary and decimal integers. The was an advanced IC for its time, pushing the limits of period manufacturing technology.
Initial yields were extremely low. Due to a shortage of chips, IBM did not actually offer the as an option for the PC until it had been on the market for six months. Development of the led to the Daasheet standard for floating-point arithmetic. There were later x87 coprocessors for the not used in PC-compatibles,and SX processors.
Starting with thethe later Intel x86 processors did not use a separate floating point coprocessor; floating point functions were provided integrated with the processor. Intel had previously manufactured the Arithmetic processing unitand the Floating Point Processor. These were designed for use with or similar processors and used an 8-bit data bus. The was initially conceived by Bill Pohlman, the engineering manager at Intel who oversaw the development of the chip.
Bill took steps to be sure that the chip could support a yet-to-be-developed math chip. In Pohlman got the go ahead to design the math chip. Bruce Ravenel was assigned as architect, and John Datashete was hired to be co-architect and mathematician for the project.
The two came up with a revolutionary design with 64 bits of mantissa and 16 bits of exponent for the longest format real number, with a stack architecture CPU and 8 bit stack registers, with a computationally rich instruction datashset.
The design solved a few outstanding known problems in numerical computing and numerical software: Palmer credited William Kahan ‘s writings on floating point as a significant influence on their design. The design initially met a cool reception in Santa Clara due datsaheet its aggressive design. Eventually, the design was assigned to Intel Israel, and Rafi Nave was assigned to lead the implementation of the chip.
Palmer, Ravenel and Nave were awarded patents for the design. It worked in tandem with the or and introduced about 60 new instructions.
The binary encodings for all instructions begin with the bit patterndecimal 27, the same as the ASCII character ESC although in the higher order bits of a byte; similar instruction prefixes are also sometimes referred to as ” escape codes “. The instruction mnemonic assigned by Intel for these coprocessor instructions is “ESC”. For an instruction with a memory operand, if the instruction called for the operand to be read, the would take the word of data read by the main CPU from the data bus.
If the operand to be read was longer than one word, the would also copy the address from the address bus; then, after completion of the data read cycle driven by the CPU, the would immediately use DMA to take control of the bus and transfer the additional bytes of the operand itself.
If an instruction with a memory operand called for that operand to be written, the would ignore the read word on the data bus and just copy the address, then request DMA and write the entire operand, in the same way that it would read the end of an extended operand. As a consequence of this design, the could only operate on operands taken either from memory or from its own registers, and any exchange of data between the and the or was only via RAM.
The main CPU program continued to execute while the executed an instruction; from the perspective datashewt the main or CPU, a coprocessor instruction took only as long as the processing of the opcode and any memory operand cycle 2 clock cycles for no operand, 8 clock cycles plus the EA calculation time [5 to 12 clock cycles] for a memory operand [plus 4 more clock cycles on an ], to transfer the second byte of the operand wordafter which the CPU would begin executing the next instruction of the program.
Thus, a system with an was capable of true parallel processing, performing one operation in the integer ALU of the main CPU while at the same time performing a floating-point operation in the coprocessor. It is not necessary to use a WAIT instruction before an operation if the program uses other means to ensure that enough time elapses between the issuance of timing-sensitive instructions so that the can never receive such an instruction before it completes the previous one.
It is also not necessary, if a WAIT is used, that it immediately precede the next instruction. Because the instruction prefetch queues of the and make the time when an instruction is executed not always the same as the time it is fetched, a coprocessor such as the cannot determine when an instruction for itself is the next instruction to be executed purely by watching the CPU bus.
The and have two queue status signals which are connected to the coprocessor to allow it to synchronize with the CPU’s internal timing of execution of instructions from its prefetch queue. The maintains its own identical prefetch queue, jntel which it reads the coprocessor opcodes that it actually executes. Because the and prefetch queues are different sizes and have different management algorithms, the determines which type of CPU it is attached to by observing a certain CPU bus line when the system is reset, and the adjusts its internal instruction queue accordingly.
The redundant duplication of prefetch queue hardware in the CPU and the coprocessor is inefficient in terms of power usage and total die area, but it allowed the coprocessor interface to use very few dedicated IC pins, which was important. At the time when thewhich defined the coprocessor interface, was introduced, IC packages with more than 40 pins were rare, expensive, and wrangled with problems such as excessive lead capacitance, a major limiting datasheer for signalling speeds.
The coprocessor operation codes are encoded in 6 bits across 2 bytes, beginning with the escape sequence:. The datashwet three Xs are the first three bits of the datashfet point opcode. Then two Ms, then the latter half three bits of the floating point opcode, followed by three Rs. The Ms and Rs specify the addressing mode information.
Application programs had to be infel to make use of the special floating point instructions. At run time, software could detect the coprocessor and use it for floating point operations. When detected absent, similar floating point functions had to be calculated in software or the whole coprocessor could be emulated in software for more precise numerical compatibility.
The x87 family does not use a directly addressable register set such as the main registers of the x86 processors; instead, the x87 registers form an eight-level deep stack structure  ranging from st0 to st7, where st0 is the top.
The x87 instructions operate by pushing, calculating, and popping values on this stack. However, dyadic operations such as FADD, FMUL, FCMP, and so on may either implicitly use the topmost st0 and st1, or may use st0 together with an explicit memory operand or register; the st0 register may thus be used as an accumulator i.
This makes the x87 stack usable as seven freely addressable registers plus an accumulator.
(PDF) 8087 Datasheet download
This is especially applicable on superscalar dayasheet processors Pentium of and later where these exchange instructions are optimized down to a zero clock penalty.
When Intel designed theit aimed to make a standard floating-point format for future designs. An important aspect of the from a historical perspective was that it became the basis for the IEEE floating-point standard.
The did not implement the eventual IEEE standard in all its details, as the standard was not finished untilbut the did. The handles infinity values by either affine closure or projective closure selected via the status register. With affine closure, positive and negative infinities are treated as different values. With projective closure, infinity is treated as an unsigned representation for very small or very large numbers.
However, projective closure was dropped from 80877 later formal issue of IEEE The retained projective datsaheet as an option, but the and subsequent floating point processors including the only supported affine closure. The differed from subsequent Intel coprocessors in that it was directly connected to the address and data buses.
The looked for instructions that commenced with the ” sequence and acted on them, immediately requesting DMA from the main CPU as necessary to access memory operands longer than one word 16 bitsthen immediately releasing bus control back to the main CPU. The coprocessor did not hold up execution of the program until the coprocessor instruction was complete, and the program had to explicitly synchronize the two processors, as explained above in the ” Design and development ” section.
Inrel was a potential crash problem if the coprocessor instruction failed to decode to one that the coprocessor understood. This yielded an execution time penalty, but the potential crash problem was avoided because the datasheeg processor would ignore the instruction if the coprocessor refused to accept it. The was able to detect whether it was connected imtel an or an by monitoring the data bus datashret the reset cycle. In practice, there was the potential for program failure if the coprocessor issued a new instruction before the last one had completed.
All models of the had a 40 pin DIP package and operated on 5 volts, consuming around 2. Unlike later Intel coprocessors, the had to run at the same clock speed as the main processor. Just as the and processors were superseded by later parts, so was the superseded. Other Intel coprocessors were the, and the Starting with thethe later Intel processors did not use a separate floating point coprocessor; virtually all included it on the main processor die, with the significant exception of the SX which was a modified DX with the FPU disabled.
Datasheet(PDF) – Intel Corporation
The was in fact a full blown DX chip with an extra pin. From Wikipedia, the free encyclopedia. Intel Intel Math Coprocessor. Intel AMD  Cyrix . Retrieved 1 December Archived from the original on 30 September Retrieved from ” https: Intel microprocessors Intel x86 microprocessors Floating point Coprocessors.
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Discontinued BCD oriented 4-bit