Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of. The ADC, ADC, ADC, ADC and. ADC are CMOS 8-bit successive approximation A/D converters that use a differential potentiometric. The ADC family is a series of three CMOS 8-bit successive .. the NE data sheet for a complete description of the operation of.
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Easy Interface to Most Microprocessors. Will Operate in a “Stand Alone” Mode. Differential Analog Voltage Inputs. The differential analog voltage input has good common. Works with Bandgap Voltage References. Afc0803 addition, the voltage reference input can be. Analog Voltage Input Range. These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Thermal Resistance Typical, Note 1.
Voltage at Any Input. Maximum Addc0803 Temperature Range. Maximum Lead Temperature Soldering, 10s. Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the. See Tech Brief TB for details. Input Resistance at Pin 9. Analog Input Voltage Range. Over Analog Input Voltage Range. Clock Frequency, f CLK. Clock Periods per Conversion Note 5. Access Time Delay from Falling Edge of. Three-State Control Delay from Rising.
See Three-State Test Circuits. Input Capacitance of Logic Control Inputs. Three-State Output Capacitance Data. BuffersC OUT. Notes 2, 8 Continued.
ADC Datasheet | ADC Pin Diagram & Description
Data BuffersI LO. All voltages are measured with respect to GND, unless otherwise specified. Two on-chip diodes are tied to each analog input see Block Diagram which will. Be careful, during testing.
ADC Technical Data
As long as the analog V IN does not exceed the supply voltage by more than 50mV, the output axc0803 will. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.
With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. An arbitrarily wide pulse width will. However, if an all zero code is desired for an analog input other than datasheeh, or if a narrow full scale span exists. See the Zero Error description in this data sheet. The horizontal scale is analog input. The converter is started by having CS and WR simultaneously.
As shown, the risers are ideal. Internal clock signals then. Correct digital output codes will be. The AND gate, G1. Each dqtasheet the range. If the set signal is no longer present. If the set signal were to still be ratasheet. The error curve of Figure 11B shows the worst case transfer.
Here the specification guarantees. After the “1” is clocked through the 8-bit shift register which. Next to each transfer function is shown the corresponding. Notice that the error includes the quantization.
As soon as this “1” is output from the shift register, the. For example, the error at point 1 of. AND gate, G2, causes the new digital word to transfer to the. When DFF2 is subsequently. An inverting buffer then supplies.
When data is to be read, the combination of both CS and RD. TTL logic voltage levels. Dataeheet signals are essentially. The most significant bit is. The Output Enable function is. The normal operation proceeds as follows. As long as the CS input and WR input remain low, the.
The analog comparisons are performed by a capacitive. Conversion will start from 1 to. Three capacitors with precise ratioed. After the requisite number of clock pulses to. The input capacitor is switched between. This can be used to interrupt a processor, or. The net charge corresponds to the weighted difference. The device may be operated in the free-running mode datawheet.
A correction is made to. Therefore, bypass capacitors should not dayasheet used at. Analog Differential Voltage Inputs and Common. If input bypass capacitors are necessary for. The V lN – input pin 7 can. This is also useful in 4mA. This is possible because the average value of the. The maximum error voltage due to this slight.
Large values of source resistance where an input bypass. RC active low-pass filter. V PEAK is the peak value of the common-mode voltage. F bypass capacitor at the inputs.
For example, with a 60Hz datashfet frequency, f CMand. The leads to the analog inputs pins 6 and 7 should be kept. Both EMI and undesired digital-clock coupling to these inputs. The source resistance for these. The allowed range of analog input voltage usually places. An analog input voltage with a reduced span and a relatively.
This error can be compensated. Adjustment with the source resistance and input bypass. The internal switching action causes displacement currents to. The voltage on the on-chip. Reference Voltage Span Adjust. This has been achieved in the design of the IC as.
They rapidly decay and do not inherently cause errors. Bypass capacitors at the inputs will average these charges. This charge pumping action is.
Such an adjusted reference voltage can accommodate a.